DS3105LN+【PDF 10/124 页】IC TIMING LINE CARD 64-LQFP

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DS3105

107

9.3

JTAG Instruction Register and Instructions

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the

TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in

the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A

rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-

IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction

parallel output. Table 9-1 shows the instructions supported by the DS3105 and their respective operational binary

codes.

Table 9-1. JTAG Instruction Codes

INSTRUCTIONS

SELECTED REGISTER

INSTRUCTION CODES

SAMPLE/PRELOAD

Boundary Scan

010

BYPASS

Bypass

111

EXTEST

Boundary Scan

000

CLAMP

Bypass

011

HIGHZ

Bypass

100

IDCODE

Device Identification

001

SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This

instruction supports two functions. First, the digital I/Os of the device can be sampled at the boundary scan

shifted into the boundary scan register through JTDI using the Shift-DR state.

EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in

the instruction register, the following actions occur: (1) Once the EXTEST instruction is enabled through the

Update-IR state, the parallel outputs of the digital output pins are driven. (2) The boundary scan register is

connected between JTDI and JTDO. (3) The Capture-DR state samples all digital inputs into the boundary scan

BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI is connected to JTDO

through the 1-bit bypass register. This allows data to pass from JTDI to JTDO without affecting the device’s normal

operation.

IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the device identification

following entry into the Capture-DR state. Shift-DR can be used to shift the ID code out serially through JTDO.

During Test-Logic-Reset, the ID code is forced into the instruction register’s parallel output.

HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI

and JTDO.

CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass

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